We are looking for a Layout Engineer to be part of the team developing the RF MEMS switches and die development. In this role you will be responsible for full chip floor-planning and layout as well as cell level and top level layout verification and documentation.

Top Reasons to Work with Us:

• Challenging work in a growing company.
• Opportunity to work on highly-innovative and challenging projects.
• Career and professional development opportunities.

Responsibilities:

• Full chip layout of RF MEMS on our own developed MEMS process using MENTOR Pyxis tools
• Floorplanning and custom layout of cells and verification against design rules.
• Mask design work.

What You Need for this Position:

MUST HAVE:

• Eng or MSc degree (electronics engineering, mathematics, or science).
• At least 2 years of relevant mask design/layout experience.
• Experience running and debugging DRC and LVS with Mentor Graphics Calibre tools.
• Be able to estimate area and time budget for full chip layout, including cell blocks and full chip integration.
• Team player, Good communication skills and cultural awareness are a must.

NICE TO HAVE:

• Some CAD knowledge, skill/python/TCL or other language experience to automate layout generation.
• RFIC passives knowledge.
• MEMS basic knowledge.
• Good level in English and French.

Softwares & EDA tools:

• CADENCE-Virtuoso or MENTOR-Pyxis,
• CALIBRE DRC/LVS

Send Applications to : [email protected]